Computer System Architecture Unit 5

Hardware layer

The hardware of the computer is usually divided into three major parts, the central processing unit (CPU) contains an arithmetic and logic unit for manipulating data, a number of registered for storing data, and control circuits for fetching and executing instructions. The memory of a computer contains storage for instructions and data. It is called a random access memory (RAM) because the CPU can access any location in memory at random and retrieve the binary information within a fixed interval of time.

The input and output processor (IOP) contains electronic circuits for communicating and

Controlling the transfer of information between the computer and the outside world. The input and output devices connected to the computer include keyboards, printers, terminals, magnetic disk drives, and other communication devices.

Computer Organization is concerned with the hardware components operate and the way they connected together to form a computer system.

Computer Architecture is concerned with the structure and behavior of the computer. It includes the information formats, the instruction set, and the techniques for addressing memory. The architectural design of the system is concerned with the specifications of the various functional modules, such as processors and memories, and structuring them together into computer system.

Input-Output Interface

Peripherals are electromechanical and electromagnetic devices and their manner of operation is different from the operation of the CPU and memory, which are electronic devices. The data transfer rate of peripherals is usually slower than the transfer rate of the CPU. The operating modes of peripherals are different from each other and must be controlled so as not to disturb the operation of other peripherals connected to the CPU.

To resolve these differences, computer systems include special hardware components between the CPU and peripherals to supervise and synchronize all inputs and output transfers. These components are called interface units because they interface between the processor bus and the peripheral device.

 

I/O Bus and Interface Modules

Each peripheral has its own controller that operates the particular electromechanical device. For example, the printer controller controls the paper motion, the print timing, and the selection of printing characters. The I/O bus from the processor is attached to all peripheral interfaces. To communicate with the particular device, the processor places a device address on the address lines. When the interface detects its own address, it activates a path between the bus lines and the device that it controls. The address is available in the address lines; the processor provides a function code in the control lines.

The interface selected responds to the function code and proceeds to execute it. The function code is referred to as an I/O Command. There are four types of commands that an interface may receive.

A control command is issued to activate the peripheral and to inform it what kind of operation to do.

A status command is used to test various status conditions in the interface and the peripherals.

A data output command causes the interface to respond by transferring data from the bus into one of its registers.

A data input command interface receives an item of data from the peripherals and places it in its buffer register.

 

 

Modes of Tranfer

Binary information received from external devices is usually stored in memory for later processing. The CPU merely executes the I/O instructions and may accept data temporarily, but the ultimate source or destination is the memory unit. Data transfer between the central computer and I/O devices may be handled in variety of modes.

Some modes use the CPU as an intermediate path; others transfer the data directly to and from the memory unit. Data transfer to and from peripherals may be handled in one of three possible modes:

    

•Programmed I/O

•Interrupt-initiated I/O

•Direct Memory Access (DMA)

 

Overview

I/O Techniques	No Interrupts	Uses of Interrupts
I/O-to-memory transfer Through processor	Programmed I/O	Interrupt-driven I/O
Direct I/O-to-memory Transfer	----------	Direct memory access (DMA).

 

The following flowchart gives an example of the use of programmed I/O to read in a block of data from a peripheral device (e.g., a record from tape) into memory. Data are read in one word (e.g., 16 bits) at a time. For each word that is read in, the processor must remain in a status-checking cycle unit it determines that the word is available in the I/O module's data register. This flowchart highlights the main disadvantage of this technique: It is a time-consuming process that keeps the processor busy.

 

        Programmed I/O

 

 

 

 

 

 

 

                    

 

 

 

 

 

 

 

Programmed I/O

 

In the programmed I/O method, the I/O device does not have direct access to memory. Transferring data under program control requires constant monitoring of the peripheral by the CPU. In the programmed I/O method, the CPU stays in a program loop until the I/O unit indicates that it is ready for data transfer.

Each byte is read into a CPU register and then transferred to memory with a store instruction. A common I/O programming task is to transfer a block of words from an I/O device and store them in a memory buffer.

The programmed I/O method is particularly useful in small low-speed computers or in systems that are dedicated to monitor a device continuously.

 

Interrupt-initiated I/O

An alternative to the CPU constantly monitoring the flag is to let the interface inform the computer when it is ready to transfer data.
This mode of transfer uses interrupt facility. The CPU responds to the interrupt signal by storing the return address from the program counter into a memory stack and then control branches to a service routine that processes the required I/O transfer. The way that the processor chooses the branch address of the service routine varies from one unit to another.

 

In principle, there are two methods, vectored interrupt and non-vectored interrupt.

In non-vectored interrupt, the branch address is assigned to a fixed location in memory.

In vectored interrupt, the source that interrupts supplies the branch information to the computer.

The following flowchart shows the use of interrupt I/O for reading in a block of data. Compare this with programmed I/O. Interrupt I/O is more efficient than programmed I/O because it eliminates needless waiting. However, interrupt I/O still consumes a lot of processor time, because every word of data that goes from memory to I/O module or from I/O module to memory must pass through the processor.

 

When an I/O device completes an I/O operation, the following sequence of hardware events occurs:

 

1. The device issues an interrupt signal to the processor.
   
2. The processor finishes execution of the current instruction before responding to the interrupt
   
3. The processor tests for an interrupt, determines that there is one, and sends an acknowledgment signal to the device that issued the interrupt. The acknowledgement allows the device to remove its interrupt signal.
   
4. The processor now needs to prepare to transfer control to the interrupt routine. To begin, it needs to save information needed to resume the current program at the point of interrupt. The minimum information required is (a) the status of the processor, which is contained in a register called the program status word (PSW), and (b) the location of the next instruction to be executed, which is contained in the program counter.
   
5. The processor now loads the program counter with the entry location of the interrupt-handling program that will respond to this interrupt. If there is more than one interrupt-handling routine, the processor must determine which one to invoke. This information may have been included in the original interrupt signal, or the processor may have to issue a request to the device that issued the interrupt to get a response that contains needed information.
   
6. At this point, the program counter and PSW relating to the interrupted program have been saved on the system stack. The contents of the processor registers need to saved, because the interrupt handler may use these registers. So all these values, plus any other state information, need to be saved. The interrupt handler will begin by saving the contents of registers on the stack.
   
7. The interrupt handler next processes the interrupt. This includes an examination of status information relating to the I/O operation or other event that caused an interrupt.
   
8. When interrupt processing is complete, the saved register values are retrieved from the stack and restored to the registers
   
9. The final act is to restore the PSW and program counter values from the stack. As a result, the next instruction to be executed will be from the previously interrupted program.
   

 

Thus the interrupt can occur at any time and therefore at any point in the execution of the user program.

 

 

 

 

 

 

 

 

        Interrupt-Driven I/O

 

 

 

 

 

 

 

 

 

                

 

 

 

 

 

 

 

 

 

Direct memory Access (DMA)

During DMA transfer, the CPU is idle and has no control of the memory buses.

DMA controller takes over the buses to manage the transfer directly between the I/O device and memory. The CPU may be placed in an idle state in a variety of ways. One common method is to disable the buses through special control signals.

 

 

 

        CPU bus signals for DMA transfer

 

 

 

 

The bus request (BR) input is used by the DMA controller to request to control of the buses. When this input is active, the CPU terminates the execution of the current instruction and places the address bus, the data bus and read and writes lines into a high-impedance state. The high-impedance state behaves like an open circuit, which means that the output is disconnected and does not logic significance. The CPU activates the bus grant (BG) output to inform the external DMA that the buses are in high-impedance state. When the DMA takes control of the bus system, it communicates directly with the memory. The data transfer may be done directly between the device and memory under control of DMA.

 

 

 

                        

 

 

DMA transfer is very useful in many applications. It is used for fast transfer of information between magnetic disks and memory. It is also useful for updating the display in an interactive terminal. Typically, an image of the screen display of the terminal is kept in memory, which can be updated under program control. The contents of the memory can be transferred to the screen periodically by means of DMA transfer.

 

This diagram shows the block diagram of a typical DMA controller. The Unit communicates with the CPU via the data bus and control lines. The CPU through the address bus selects the registers in the DMA by enabling the DS (DMA select) and RS (register select) inputs. The RD (read) and WR (write) inputs are bidirectional. When the BG (bus grant) input is 0, the CPU can communicate with the DMA registers through the data bus to read from or write to the DMA registers. When BG = 1, the CPU has relinquished the buses and DMA can communicate directly with the memory by specifying an address in the address bus and activating the RD or WR control.

The DMA controller has three registers: an address register, a word count register, and a control register. The address register contains an address to specify the desired location in memory. The address bits go through bus buffers into the address bus. The CPU can read from or write into the DMA registers under program control via the data bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

                            

 

 

 

 

 

 

 

 

        DMA transfer in a computer system

 

 

 

 

 

 

 

 

 

 

 

 

DMA transfer

From the above diagram, the CPU communicates with the DMA through the address and data buses as with any interface unit. The DMA has its own address, which activates the DS and RS lines. The CPU initializes the DMA through the data bus. Once the DMA receives the start control command, it can start the transfer between the peripheral device and the memory.

    When the peripheral device sends a DMA request, the DMA controller activates the BR line, informing the CPU to relinquish the buses. The CPU responds with its BG line, informing the DMA that its buses are disabled. The DMA then puts the current value of its address register into the address bus, initiates the RD or WR signal, and sends a DMA acknowledge to the peripheral device. Note that the RD and WR lines in the DMA controller are bi-directional. The direction of transfer depends on the status of the BG line.

    When BG = 0, the RD and WR are input lines allowing the CPU to communicate with the internal DMA registers.

    When BG = 1, the RD and WR are output lines from the DMA controller to the random-access memory to specify the read or write operation for the data.

When the peripheral device receives a DMA acknowledge, it puts a word in the data bus (for write) or receives a word from the data bus (for read). Thus the DMA controls the read or write operations and supplies the address for the memory. For each word that is transferred, the DMA increments its address registers and decrements its word count registers.

If the word count does not reach zero, the DMA checks the request line coming from the peripheral. For a high-speed device, the line will be active as soon as the pervious transfer is completed. If the peripheral speed is slower, the DMA request line may come somewhat later.

If the word count register reaches zero, the DMA stops any further transfer and removes its bus request. It also informs the CPU of the termination by means of an interrupt.

When the CPU responds to the interrupt, it reads the content of the word count register. The zero value of this register indicates that all the words were transferred successfully. The CPU can read this register at any time to check the number of words already transferred.

 

 

 

 

 

 

I/O Processor (IOP)

The IOP is similar to a CPU except that it is designed to handle the details of I/O processing. IOP instructions are designed to facilitate I/O transfers. It can perform other processing task, such as arithmetic, logic, branching, and code translation.

 

 

 

 

 

 

The block diagram of a computer with two processors is shown above. The memory unit occupies a central position and can communicate with each processor by means of direct memory access. The CPU is responsible for processing data needed for computational tasks. The data formats of peripheral devices differ from memory and CPU data formats. Data are gathered in the IOP at the device rate and bit capacity while the CPU is executing its own program. The communication between the IOP and the devices attached to it is similar to the program control method of transfer. The way by which the CPU and IOP communicate depends on the level of the sophistication included in the system. In most computer systems, the CPU is the master while the IOP is a slave processor.

Instructions that are read from memory by an IOP are sometimes called commands, to distinguish them from instructions that are read by the CPU. Otherwise, an instruction and a command have similar functions. Commands are prepared by experienced programmers and are stored in memory. The command words constitute the program for the IOP. The CPU informs the IOP where to find the commands in memory when it is time to execute the I/O program.

 

 

 

CPU-IOP Communication

The communication between CPU and IOP may take different forms, depending on the particular computer considered. The CPU sends an instruction to test the IOP path.

The IOP responds by inserting a status word in memory for the CPU to check.

The CPU refers to the status word in memory to decide what to do next.

The IOP takes care of the data transfers between several I/O units and the memory while the CPU is processing another program

 

                CPU-IOP communication

 

 

     CPU Operation                 IOP Operation

 

 

 

    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

    Continue

The sequence of operations may be carried out as shown in the above flowchart. The CPU sends an instruction to test the IOP path. The IOP responds by inserting a status word in memory for the CPU to check. The bits of the status word indicate the condition of the IOP and I/O device, such as IOP overload condition, device busy with another transfer, or device ready for I/O transfer.

 

The CPU refers to the status word in memory to decide what to next.

The CPU sends the instruction to start I/O transfer.

The memory address received with this instruction tells the IOP where to find its program.

The CPU can now continue with another program while the IOP is busy with the I/O program.

Both programs refer to memory by means of DMA transfer.

When the IOP terminates the execution of its program, its sends the interrupt request to the CPU.

The CPU responds to the interrupt by issuing an instruction to read the status from the IOP.

The IOP responds by placing the contents of its status report into the specified location.

The status word indicates whether the transfer has been completed or if any errors occurred during the transfer.

The IOP takes care of all data transfers between several I/O units and the memory while the CPU is processing another program.

 

I/O Interrupts

External interrupts come from input-output (I/O) devices, from timing devices, from a circuit monitoring the power supply, or from any other external source.

For example external interrupts are I/O device requesting transfer of data, I/O finished transfer of data, elapsed time of an event, or power failure. Timeout interrupt may result from a program that is in an endless loop and thus exceeded its time allocation.

Power failure interrupt may have its service routine a program that transfers the state of the CPU into a nondestructive memory in the few milliseconds before power ceases